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Self-timed circuits as a basis for developing next generation high-reliable high-performance computers

https://doi.org/10.17073/1609-3577-2020-4-277-281

EDN: PEIHYV

Abstract

The paper proposes design and circuitry solutions for the implementation of high-performance next generation computers. They are based on self-timed circuit design methodology and provide an increase in the tolerance of computing systems to soft errors resulting from induced noises and radiation exposure.

About the Authors

A. A. Zatsarinnyy
Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences
Russian Federation

44-2 Vavilov Str., Moscow 119333

Alexandеr A. Zatsarinnyy — Dr. Sci. (Eng.), Chief Researcher, Deputy Director



Yu. A. Stepchenkov
Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences
Russian Federation

44-2 Vavilov Str., Moscow 119333

Yury A. Stepchenkov — Cand. Sci. (Eng.), Department Head



Yu. G. Diachenko
Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences
Russian Federation

44-2 Vavilov Str., Moscow 119333

Yury G. Diachenko — Cand. Sci. (Eng.), Senior Researcher



Yu. V. Rogdestvenski
Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences
Russian Federation

44-2 Vavilov Str., Moscow 119333

Yury V. Rogdestvenski — Cand. Sci. (Eng.), Leading Researcher



References

1. Stepchenkov Y. A., D’yachenko Y. G., Gorelkin G. A. Selfsynchronous circuits are the future of microelectronics. Voprosy radioelektroniki = Questions of Radio Electronics. 2011, vol. 4, no. 2, pp. 153—184.

2. Stepchenkov Yu. A., Denisov A. N., Dyachenko Yu. G., Grinfeld F. I., Filimonenko O. P., Morozov N. V., Stepchenkov D. Yu., Plekhanov L. P. Library functional cells for the design of self-synchronous semi-custom BMK microcircuits of the 5503/5507 series. Moscow: Technosfera, 2017. 367 p. (In Russ.). URL: http://www.technosphera.ru/lib/book/497

3. Tailor R. A., Reese R. B. Uncle—Unified NCL Environment—an NCL design tool. Ch. 14. In: Di J., Smith S. C. (Eds) Asynchronous Circuit Applications. 2019. Pp. 293—307. DOI: 10.1049/PBCS061E_ch14

4. Pat. No. 2718220 (RF). Formirovatel’ parafaznogo signala s yedinichnym speyserom [Paraphase signal former with a single spacer]. A. A. Zatsarinnyy, S. V. Kozlov, Yu. A. Stepchenkov, Yu. G. Dyachenko, 2020. Bul. No. 10. (In Russ.). URL: https://yandex.ru/patents/doc/RU2718220C1_20200331

5. Stepchenkov Y. A., Kamenskih A. N., Diachenko Y. G., Rogdestvenski Y. V., Diachenko D. Y. Improvement of the natural self-timed circuit tolerance to short-term soft errors. Advances in Science, Technology and Engineering Systems Journal. 2020, vol. 5, no. 2, pp. 44—56. DOI: 10.25046/aj050206

6. Stepchenkov Y., Rogdestvenski Y., Kamenskih A., Diachenko Y., Diachenko D. Improvement of the quasi delay-insensitive pipeline noise immunity. Proc. 11th International Conference on Dependable Systems, Services and Technologies (DESSERT). Kyiv, Ukraine, 14–18 May, 2020. IEEE, 2020. Pp. 47—51. DOI: 10.1109/DESSERT50317.2020.9125021

7. Sokolov I., Stepchenkov Yu., Diachenko Yu., Rogdestvenski Yu., Diachenko D. Increasing self-timed circuit soft error tolerance. Proc. EastWest Design & Test Symposium (EWDTS). Varna, Bulgaria, September 4–7, 2020. Varna, 2020. Pp. 450—454. DOI: 10.1109/EWDTS50664.2020.9224705


Review

For citations:


Zatsarinnyy A.A., Stepchenkov Yu.A., Diachenko Yu.G., Rogdestvenski Yu.V. Self-timed circuits as a basis for developing next generation high-reliable high-performance computers. Izvestiya Vysshikh Uchebnykh Zavedenii. Materialy Elektronnoi Tekhniki = Materials of Electronics Engineering. 2020;23(4):277-281. (In Russ.) https://doi.org/10.17073/1609-3577-2020-4-277-281. EDN: PEIHYV

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ISSN 1609-3577 (Print)
ISSN 2413-6387 (Online)