Fault-tolerant self-timed counters
A. A. Zatsarinnyy,
Yu. A. Stepchenkov,
Yu. G. Diachenko,
D. V. Khilko,
G. A. Orlov,
D. Yu. Diachenko https://doi.org/10.17073/1609-3577j.met202310.588
Abstract
The article studies the fault-tolerant self-timed (ST) counter design problem. Combinational ST circuits have a higher fault tolerance in comparison with synchronous counterparts due to redundant information coding and mandatory acknowledging of the completion of all initiated circuit cells' switches. Sequential ST circuits, including counters, are more sensitive to failures due to the presence of memory cells, the state of which can change under the influence of a failure and be remembered. For their fault-tolerant implementation, special circuitry methods, namely DICE and Quatro, are used. They are similar to the data processing channel duplication, but use transistor cross-connection in the circuit cells. This approach significantly reduces the likelihood of a change in the counter bit's state due to a failure. The article proposes DICE-type and Quatro-type ST counter cases, compares their features and resumes recommendations for the fault-tolerant ST counter implementation.
Keywords
Supporting agencies: The study was carried out within the framework of a grant from the Russian Science Foundation (project No. 22-19-00237).
About the Authors
A. A. Zatsarinnyy
Federal Research Centre “Information and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilov Str., Moscow 119333
Alexandеr A. Zatsarinnyy — Dr. Sci. (Eng.), Chief Researcher, Deputy Director
Yu. A. Stepchenkov
Federal Research Centre “Information and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilov Str., Moscow 119333
Yury A. Stepchenkov — Cand. Sci. (Eng.), Head of Department, Federal Research Centre “Information and Control” of the Russian Academy of Sciences
Yu. G. Diachenko
Federal Research Centre “Information and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilov Str., Moscow 119333
Yury G. Diachenko — Cand. Sci. (Eng.), Senior Researcher
D. V. Khilko
Federal Research Centre “Information and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilov Str., Moscow 119333
Dmitry V. Khilko — Senior Researcher
G. A. Orlov
Federal Research Centre “Information and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilov Str., Moscow 119333
Georgy A. Orlov — Junior Researcher
D. Yu. Diachenko
Federal Research Centre “Information and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilov Str., Moscow 119333
Denis Yu. Diachenko — Research Engineer
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Review
For citations:
Zatsarinnyy A.A., Stepchenkov Yu.A., Diachenko Yu.G., Khilko D.V., Orlov G.A., Diachenko D.Yu. Fault-tolerant self-timed counters. Izvestiya Vysshikh Uchebnykh Zavedenii. Materialy Elektronnoi Tekhniki = Materials of Electronics Engineering. 2024;27(2):125-131. (In Russ.) https://doi.org/10.17073/1609-3577j.met202310.588
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