Failure-tolerant synchronous and self-timed circuits comparison
https://doi.org/10.17073/1609-3577-2021-4-229-233
Abstract
The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits’ failure tolerance.
Keywords
synchronouscircuit,
self-timedcircuit,
softerror,
failuretolerance,
triple modular redundancy,
duplication,
reliability
Supporting agencies: The work was carried out within the framework of the state assignment No. 0063-2019-0010.
About the Authors
A. A. Zatsarinny
Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilova Str., Moscow 119333
Alexandеr A. Zatsarinny — Dr. Sci. (Eng.), Chief Researcher, Deputy Director
Yu. A. Stepchenkov
Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilova Str., Moscow 119333
Yury A. Stepchenkov — Cand. Sci. (Eng.), Department Head
Yu. G. Diachenko
Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilova Str., Moscow 119333
Yury G. Diachenko — Cand. Sci. (Eng.), Senior Researcher
Yu. V. Rogdestvenski
Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences
Russian Federation
Russian Federation
44-2 Vavilova Str., Moscow 119333
Yury V. Rogdestvenski — Cand. Sci. (Eng.), Leading Researcher
References
1. Viktorova V.S., Lubkov N.V., Stepanyants A.S. Reliability analysis of fault-tolerant control computing systems. Moscow: Institute for Control Problems of the Russian Academy of Sciences; 2016. 117 p. (In Russ.). https://www.ipu.ru/sites/default/files/card_file/VLS.pdf (accessed: 08.06.2021).
2. Alagoz B.B. Boolean Logic with Fault Tolerant Coding. OncuBilim Algorithm and Systems Labs. 2009. V. 09, Art. No 03.
3. Dubrova E. Fault-tolerant design. KTH Royal Institute of Technology, Krista, Sweden, 2013, Springer, 185 p. https://doi.org/10.1007/978-1-4614-2113-9
4. Zakharov V., Stepchenkov Y., Diachenko Y., Rogdestvenski Y., Self-Timed Circuitry Retrospective. International Conference Engineering Technologies and Computer Science EnT. Moscow (Russia), 24–27 June 2020, pp. 58—64.
5. Stepchenkov Y.A., Kamenskih A.N., Diachenko Y.G., Rogdestvenski Y.V., Diachenko D.Y. Fault-tolerance of self-timed circuits. 10th International Conference on Dependable Systems, Services, and Technologies (DESSERT), 2019. https://doi.org/10.1109/DESSERT.2019.8770047
6. Stepchenkov Y.A., Kamenskih A.N., Diachenko Y.G., Rogdestvenski Y.V., Diachenko D.Y. Improvement of the natural self-timed circuit tolerance to short-term soft errors. Advances in Science, Technology and Engineering Systems Journal. 2020; 5(2): 44—56. https://doi.org/10.25046/aj050206
7. Zatsarinny A.A., Stepchenkov Yu.A., Diachenko Yu.G., Rogdestvenski Yu.V. Self-timed circuits as a basis for developing next generation high-reliable high-performance computers. Proceedings of the international conference “Mathematical modeling in materials science of electronic components” (ICM3SEC–2020). October 19–20, 2020, Moscow. Moscow: MAKS Press; 2020: 114—116. (In Russ.). https://doi.org/10.29003/m1535.MMMSEC-2020/114-116
8. Monnet Y., Renaudin M., Leveugle R. Hardening techniques against transient faults for asynchronous circuits. 11th IEEE International Conference: On-Line Testing Symposium, 2005. https://doi.org/10.1109/IOLTS.2005.30
9. Stepchenkov Yu.A., Diachenko Yu.G., Rogdestvenski Yu.V., Morozov N.V., Stepchenkov D.Yu., Diachenko D.Yu. Self-timed pipeline immunity to soft errors in its combinational part. Systems and Means of Informatics. 2020; (3(30)): 49—55. (In Russ.). https://doi.org/10.14357/08696527200305; http://selftiming.ru/new/2020/12/07/ustojchivost-samosinhronnogo-konvejera-k-logicheskim-sboyam-v-kombinaczionnoj-chasti (accessed: 08.06.2021).
10. Sokolov I.A., Stepchenkov Yu.A., Diachenko Yu.G., Rogdestvenski Yu.V. Improvement of self-timed circuit soft error tolerance. Informatics and Applications. 2020; 14(4): 63—68. (In Russ.). https://doi.org/10.14357/19922264200409; http://selftiming.ru/new/2021/02/01/povyshenie-sboeustojchivosti-samosinhronnyh-shem (accessed: 08.06.2021).
Review
For citations:
Zatsarinny A.A., Stepchenkov Yu.A., Diachenko Yu.G., Rogdestvenski Yu.V. Failure-tolerant synchronous and self-timed circuits comparison. Izvestiya Vysshikh Uchebnykh Zavedenii. Materialy Elektronnoi Tekhniki = Materials of Electronics Engineering. 2021;24(4):229-233. (In Russ.) https://doi.org/10.17073/1609-3577-2021-4-229-233
Views:
297
Email this article 