Fault-tolerant selt-timed circuits
https://doi.org/10.17073/1609-3577-2022-4-298-304
EDN: OVSYUI
Abstract
The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to faults. Redundant ST coding and two-phase discipline ensures that ST circuits are more soft error tolerant than synchronous counterparts. Duplicating ST channels instead of tripling reduces the fault-tolerant ST circuits’ redundancy and retains their reliability level compared to synchronous counterparts.
About the Authors
A. A. ZatsarinnyRussian Federation
44-2 Vavilova Str., Moscow 119333
Alexandеr A. Zatsarinny — Dr. Sci. (Eng.), Chief Researcher
Yu. A. Stepchenkov
Russian Federation
44-2 Vavilova Str., Moscow 119333
Yury A. Stepchenkov — Cand. Sci. (Eng.), Head of Department
Yu. G. Diachenko
Russian Federation
44-2 Vavilova Str., Moscow 119333
Yury G. Diachenko — Cand. Sci. (Eng.), Senior Researcher
Yu. V. Rogdestvenski
Russian Federation
44-2 Vavilova Str., Moscow 119333
Yury V. Rogdestvenski — Cand. Sci. (Eng.), Leading Researcher
L. P. Plekhanov
Russian Federation
44-2 Vavilova Str., Moscow 119333
Leonid P. Plekhanov — Cand. Sci. (Eng.), Senior Researcher
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Review
For citations:
Zatsarinny A.A., Stepchenkov Yu.A., Diachenko Yu.G., Rogdestvenski Yu.V., Plekhanov L.P. Fault-tolerant selt-timed circuits. Izvestiya Vysshikh Uchebnykh Zavedenii. Materialy Elektronnoi Tekhniki = Materials of Electronics Engineering. 2022;25(4):298-304. (In Russ.) https://doi.org/10.17073/1609-3577-2022-4-298-304. EDN: OVSYUI